The present invention generally relates to semiconductor memories, and more particularly to a semiconductor memory which can serially input or output data consecutively and is provided with two data bus lines respectively for odd bits and even bits.
Generally, in a semiconductor memory which is used in the field of image processing, there is a demand to enable both a random data access from a central processing unit (CPU) and a serial data access from a cathode ray tube (CRT). Hence, a so-called dual port memory which has a random access port and a serial access port is used in the field of image processing.
A conventional dual port memory comprises a random access memory (RAM) and a serial access memory (SAM) which is provided with a data register for holding data amounting to one word of the RAM. A serial access is made to each cell of the data register by designation of a pointer. The serial data which is obtained by the access is output as dot data. Alternatively, external serial data may be written into the data register.
A display time per pixel on a high resolution CRT is extremely short, and the display time is for example 20.9 ns per dot on a CRT having 1120.times.750 dots. For this reason, a high access speed is required of the serial access port.
Accordingly, a data bus line which connects each cell of the data register to an input/output buffer is divided into two systems, that is, a data bus line for odd bits and a data bus line for even bits. During an active period (data transfer period) in which the data bus line of one system is made active, the data bus line of the other system is set to a reset period for the following reasons. That is, if the serial transfer is carried out solely by use of the data bus line of one system, the data bus line must be reset after one bit of data is transferred and the data transfer is inevitably stopped during this reset period. But by providing two systems of data bus lines, it is possible to avoid stopping the data transfer and therefore improve the serial access speed.
A description will now be given of the resetting the data bus line. Generally, the data bus line comprises a pair of signal lines and the data transfer is made by detecting a potential difference between the pair of signal lines in a sense amplifier. In order to carry out the data transfer at a high speed, it is necessary to erase the transfer data of the previous cycle, that is, the potential difference of the previous cycle. The potential difference is cleared to zero by short-circuiting the pair of signal lines and the potentials of the pair of signal lines are both pulled up to a high level so as to erase the potential difference of the previous cycle, that is, to reset the pair of signal lines. After the reset operation is made, one of the pair of signal lines is discharged to a low level in the next cycle, and it is possible to quickly increase the potential difference between the pair of signal lines and accordingly sense the potential difference at a high speed.
However, in the conventional dual port memory, the data bus lines of the two systems are respectively set to the active period and the reset period in synchronism with a rising edge in an external serial access strobe (SAS) signal which has a duty factor of 50%. As a result, there is a limit to increasing the serial access speed for the following reasons.
FIGS.1(A) through 1(F) are timing charts for explaining the operation of the conventional dual port memory. FIG.1(A) shows the SAS signal, FIG.1(B) shows a signal on the data bus line for the odd bits, FIG.1(C) shows a signal on the data bus line for the even bits, FIG.1(D) shows multiplexed data (serial data), FIG.1(E) shows odd bit data, and FIG.1(F) shows even bit data. Each active period and each reset period of the data bus lines for the odd and even bits are respectively determined by the rising edge of the SAS signal. Hence, the active period and the reset period have identical lengths which are equal to a cycle time t.sub.sc of the SAS signal. But because the cycle time t.sub.sc cannot be made shorter than the actual active period, there is a limit to increasing the serial access speed by the reduction of the cycle time t.sub.sc. On the other hand, when the active period is set long to suit an external device, the cycle time t.sub.sc also becomes long.